Frequency difference measuring circuit



Jun e 1, 1965 2 Sheets-Sheet 1 Filed Jan. 16, 1961 FIG.|.

T l I n 1 U E U U E m UK M H H U L M J1 FEE FIG.2.

INVENTOR.

TEFANOV 6 PW ATTORNE S Bom s 8 BY *9? FIG. 3.

' June 1, 1965 B. STEFANOV 3,187,195

FREQUENCY DIFFERENCE MEASURING CIRCUIT Filed Jan. 16, 1961 2 Sheets-Sheet 2 A I TIME C l l l l 4 Q u L H 7 TIME J J J FTIME K F T LTIME FP F F H F H F FI LTIME IAFWENTOR.

' B- Boms STEFANOV F I G. 5 gymap dz'ozifw ATTORNEYS signal in which United States Patent 3,187,195 FREQEENCY DEFERENCE h EASG CCUTT Boris Stefanov, Los Angeles, Caiifi, 'assignor to Kauhe and Company, Inc., a corporation of California Filed 32m. 16, 1961, Ser. No. 82,971 2 Claims; (Cl. 307-4385) This invention relates generally to electrical circuits and more particularly to novel circuits for providing an output wave form having a frequency equal to the difference frequency of first and second input wave forms.

Circuits for generating frequency difierences are Well known inthe art. Certain types of such circuits such as employed in radio circuitry, for example, are often referred to as mixers, In addition to a frequency difference output signal, however, mixer circuits will also include in the output signal additional wave forms corresponding to the original input signals as well as the frequency sum of the input signals. As a consequence, if only the diiference frequency signalis desired, suitable filters must be employed.

Patented June 1, 1965 FIGURE 3 is a detailed circuit diagram of the first embodiment represented by certain ones of the blocks in the diagram of FIGURE 1';

FIGURE 4 illustrates a series of lettered wave forms useful in explaining the operation of a second embodiment of the invention; and, 1

FIGURE 5 is a detailed circuit diagram of the second embodiment of the invention.

Referring first to FIGURE 1, the circuit includes first and second inputs 10 and 11 for receiving firstand second input wave forms having frequencies f and f respectively. As shown, these first and second input frequencies are fed through suitable square wave generating means which may constitute overdriven amplifiers 12 and 13, respectively. The resulting first and second square wave forms are fed into a converting means 14. Aswill become clearer when the exemplary detailed circuit of FIG.- URE 3 is described, the converting means 14 provides, a time modulated output signal which changes between first .and second voltages. Thus, a first voltage is provided at the output of the converting means 14 only when the first In addition to the foregoing, presently known mixer cir- I cuits will not provide a difference frequency if the actual difference in the frequency between the input signals is relatively small; for example, of the order of one cycle per 1 second. This is because the output circuit components of the mixers are designed to pass only certain frequency ranges and when frequencies approach relatively 10 values, they appear essentially as direct currents and thus are blocked by the output components designed onlyv to pass A.-C.

With the above in mind, it is a primary object of this invention to provide novel difference frequency generating circuits in which the output wave form consists solely of a signal having a frequency corresponding to the difference in frequency of first and second input wave forms.

More particularly, it is an object to provide novel frequency difference generating circuits in which the output wave form may have a frequencyfrom zero to a value corresponding to the higher frequency input wave form signal to the end that there is thus provided a circuit means for providing a signal which may be varied in frequency from zero cycles per second 'slowly up through various frequencies to the frequency of the higher frequency input signal when the other input signal is of zero frequency.

More general objects of this invention are to provide novel frequency difference relative lengths of time that the input signals are of like polarity as compared to the reiative lcn ths of time that the signals are of unlike polarity. The time modulated signal, in turn, is then fed into an integrating means to provide an output wave form which will have a frequency corresponding to the difference in frequency of the input.

signals. A better understanding of the invention will be had by referring to two embodiments thereof as illustratedin the accompanying drawings, in which:

generating circuits meeting the foregoing objects which employ minimum numbers of the time modulation is determined'by the i and second input square wave forms are of like polarity and the second output voltageis provided when'the first and second input square wave forms are I of unlike polarity. These'first and second voltages making up the time modulated signal are passed to an integrating means 15 to provide an output wave form at 16 having afrequency f corresponding to the difference of thefrequencies f and f The above will be clearer by now referring to the various wave forms shown in FIGURE '2. These wave forms are lettered A, C, E, and Gand correspond to the wave forms appearing at the correspondingly lettered points A, C, E, and G in the block diagram of FIG- URE 1. Thus, referring to the top wave form A, this waveform constitutes a square wave function having a 7 frequency f as would appear at the output of the overdriven amplifier 12 of FIGURE 1. Similarly, the wave form C constitutes a square Wave function having a frequency f corresponding to the square wave format the output of the overdriven amplifier 13 of FIGURE l/ In the'example chosen for illustrative purposes, it will be noted that the square wave form C. has a slightly higher frequency f than the frequency of the wave form A designated f Therefore, it will be evident that by comparing the waveforms A and Cat corresponding intervals of time, there will be periods when both wave FIGURE-1 is a simplified block diagram of the basic circuit of the invention;

FIGURE 2 illustrates a series of wave forms occurring at correspondingly lettered pointsin the circuit of FIG URE 1 in accordance with a'first embodiment of the invention;

forms have the same polarity such as the casewhen both are upor of positive polarity as indicated by the levels U to the left of the diagrams or when both'are down or of negative polarity as indicated by the letters D to,

the left of the diagram. Also, there will be other periods when the wave form Ais up, and thewave form C is down and still other periods when the wave form C is up and the wave form A is down. Essentially, the con- 'verting means 14 of FIGURE I provides first and second output voltages which are determined by. the polarity relationships of the waveforms A and C at given intervals of time. v 1 v Thus, referring to the wave form B, there is shown a first voltage level designated F to the left of the diagram in FIGURE 2 and a second voltage level indicated at S and C are of opposite polarity such as indicated at the times t andt in FIGURE'Z. The Wave form .E, on the ,other hand, is down or at its first voltage; level S whenever the Waveforms A and Care of the-same polarity such as-indicated at the times t audit; in FIGURE 2..

Integration of wave form E from converter 14 by ina tegrating means 15 of FIGUREI will. thenprovide an 'output wave form as shown at G in FIGURE 2, This PNP transistors Q and Q 'dicated at 24 and 25. As shown,

of the resistances R and R vspo'nding to the wave minal :32 of the transistor Q emitter terminal 27, and to 'ground at 29.

and R will result in y ducting, current will pass from a. V 3 I output wave form represents essentially the integral of the E wave form with respect to time, and it will be immediately evidentthat the. frequency j of the output wave form G corresponds to the difierence, frequency of the input wave forms or f f a FIGURE 3 illustrates one type of converting circuit for providing the wave form.E in response to reception. of the input square wave forms A and C." Also shown in FIGURE 3 is one type of integrating circuit.

Referring first to theconverting circuit designated generally by the numeral 14 in FIGURE 3, there are provided first and second switching means in the form of As shown, these transistors respectively includeemitter terminals 17 and 18 connected through-pairs of series connected resistances R R and R R4, respectively; age B+ supplied on line 19. the" emitters 17 and 18 may be considered as input means. The outputs are provided by the collector terminals 20 and 21 connected together to 'a common output lead 22 connecting to a junction point corresponding in position to the letterE from which an output'load resistance R is connected. As shown, the other side of the resistance R is connected by lead 23 to the minus side of the voltage source designated B.

The switching transistors Q and trolled throughtheir 'base terminal connections as inthe base terminal24 for the first transistor Q connects to the junction point between resistances R and R and the base terminal 25. for the second transistor Q connectsto the junction point to a common source of voltswitching of the transistors Q andQ is effected by'means of first and second controltransistors Q are of the NPN type. As shown, these transistors have their respective emitter terminals 26 and 27 connected to a common lead 28 grounded at 29. Their collector terminals 30 and 31, in turn, are connected to the voltage source B+ on line 19 through the series pairs of resistancesR R and R R respectively. The base terminals 32 and 33 are respect vely connected to receive thefirst and second square wave forms A and C on lines .34 and 35. Base resistances R and R- connect between 'the lines 34 and 35 and common ground lead 28, respectively.

With the above described circuit, there will be provided E a time modulated signal correform E-of FIGURE 2'when the at the junction point first and second input .wave

this moment the'input wave form A is .down and the input wave form C is up. Referring to FIGURE 3, the input wave form A on;line 34 willdrive the base ternegative holding the transistor Q off or nonconducting. Simultaneously, reception of the up input wave form C on the baseterminal 33 of the transistor (1.; conducting state. Current will pass from B+ through the lead .19, R R collector terminal 31, transistor Q The flow of current through the resistances R a drop of potential at the junction point between these resistances, thereby driving the base terminal 25 of the .at the junctionfp'oint of the IQ? sistances R 1 and R sistor Q f'will remain elevated and"switching'transistor When considered as switches,

Q in turn are con- 7 The actual control of the forms A and C are provided 'on the conductors 34' andSS, respectively." The opera- 7 tion is as follows; With reference once again to ,FIG-' URE' 2, assume conditions correspond to thetime t At will switchf'this transistor to a' will remain high, and therefore the voltage, on the base terminal24 for the switching tranenemas.

, With reference to FIGURE 3, when the voltage on the and Q, which i Q will-beheld on or open; With transistor Q con-- 13+ and. lead 1-9 through the resistances R and R4, emitter terminal 13, collector terminal 2 1, and'cornmon outputlead to the junction 1 series connected coupling condenser 36 and resistance 37;

the resistance R to the negative side B.

up, and the second input wave conditions, vboth 'the control R 'Thus,'both the base line 35 changes fronrup to down, the base terminal 33 is dropped in'voltage, thereby turning olf the previously conducting transistor Q With transistor-Q cut ofi, current flow will stop throughthe resistances R 'and R and therefore their junction point will rise inpotential, thereby elevating the potential on the base terminal 25 to switch 05 the transistor Q The transistor Q will remain nonconducting since the wave form A at the time t is still down. Therefore, there will be no current flowing through the common output line 22at the junction point E through resistance R and therefore the voltage at the junction point will be at the. depressed or first lower voltage level as a consequence of the connection of this point through of the voltage source. Thisfir'st voltage level is indicated at F at the time t in the wave form E of FIGURE 2..

At the time t the wave form A has moved from down to up, andthe wave form C is still down Thus, with reference again to FIGURE; 3, when the wave form A is up, the control transistor Q will be switched on, resulting in current flowing through the resistances R and R and through. the transistor Q to the ground lead 28, thereby'causing a drop in voltage at. the junction point between the resistances R and R This drop in voltage will be passed to the base terminal 24 of the first switching transistor Q thereby switching this transistor on. Current will thus pass through the resistances R andR transistor Q common lead 22, to .the junction E and :across' resistance R to again provide a second voltage level at the junction point E. At this time t since the second input wave form C is still down, the transistor Q; is held oh? and therefore the voltage at the junction of the resistances R and R is suificiently elevated to hold the second switching transistor Q ofi.

Finally, at the time t the firstinput wave form A is form C is up. Under these transistors Q3 and Q, will be caused 'to conduct and therefore. current will flow through both the'resistances R R and the resistances R terminal leads 24 and 25 will be lowered in potential. However, the emitter terminals '17 and 18 will also be dropped in potential because of the current flow across the resistances R and R respectively,

so that the difierence between the base and emitter potentials' of the transistors Q and Qgwill not change so that the transistors Q and Q will both be held open or off.

Therefore, the voltage at the junction point B during time t; will be at its first voltage level as shown at F in the wave form E of FIGURE '2.

Summarizing the foregoing, when the polarity of the.

input wave forms'A and C are the same as at the times t and t both the switching transistors Q and Q are held ,open or in a non-conducting state. When the polarities of the input wave forms A and Care unlike as at the times t or t;,', either one or the other, of the transistors Q and Q will be caused to conduct as a consequence of a changein'the control potentialon its base through the action of oneof the control transistors Q or.Q so that a voltage'will be developedacross the resistance R at the junction point E.

The. time modulatedsignal or wave form FIGURE 2 and appearing at the. junction point E in FIGURE 3 will belpassed to the integrating circuit designated generally by-the numeral 15 through conventional As shown, the wave form passes directly to thebase terminal 33.05 a charge and discharge control transistor Q E shown in.

' E again changes from its first of the NPN type having its emitter terminal 39 grounded as shown and its collector terminal 46 connected through resistance R to B+. Connected across the base and collector terminals 38 and 41' is an integrating storage condenser 41 shunted by a relatively high resistance .R The output from the integrating circuit is taken at the point G in FIGURE 3 and is in the form of the wave form G depicted in FIGURE 2.

The operation of the integrating circuit is as follows: With the second voltage level provided on the base ter-' minal 38 as at the time t shown in FIGURE 2, for example, the transistor'Q is caused to conduct, thereby permitting any voltage across the storage condenser 41 to discharge through the collector terminal 44 transistor Q and emitter terminal 39 to ground. When the voltage levelon the base terminal 33 changes to the first voltage as at the time 1 in FIGURE 2, the transistor Q is cut off so that the condenser 41 will then commence charging from B+ voltage through the resistance R The condenser 41 will continue to charge until the voltage wave form voltage to its second voltage value as shown during the time interval at which the instant t exists in FIGURE 2. The transistor Q is thus turned on during the time interval that the second voltage exists at the base terminal 38 to permit discharging of the condenser 41 during this time. Charging of the condenser 41 will subsequently take place only after the second voltage at the base terminal 38 of the transistor Q again chan es to its first value as during the period of time at which the instant t appears in FIGURE 2.

The actual charge and discharge curves define theoutput wave form G shown in FIGURE 2 when the paths are all connected. The result is a slowly varying output wave form in which the frequency f exactly equals the difference in the frequencies f, and f; of the input wave forms. i

The minute variations in the wave form G may be readily removed by simply providing a conventional smoothing Referring now to FIGURES 4 and 5, there is illustrated a second embodiment of the invention in which diodes are employed in place of the control and switching transistors of FIGURE 3. Referring first to FIGURE 4, there are shown lettered wave forms which occur at the correspondingly lettered points in the circuit of FIGURE 5. As shown, the first and second input wave forms designated A and C are identical to the wave forms A and C shown in FIGURE 2. The third wave form H is up only when both A and C are up. The fourth wave form I is down only if both A and C are down. The wave form K is the same as wave form I with polarity inverted.

From the wave forms up anddown when H and K are both down. The signal L is the same as time modulated signal E of FIGURE 2 with polarity inverted. The first and second voltages F and S are therefore shown as inverted. From the time.

modulated signal L, there is derived the output frequency difference shown at M which ,is exactly the same as the frequency difference output signal G of FIGURE 2 except that its polarity is inverted.

The manner in which the above wave forms are derived will be evident by now referring to the circuit shown in FIGURE 5. Thus, the input wave forms A and C are received on lines 42 and 43 through reversediodes D and D to a junction point at which the wave form H is generated. The B line connects through a resistance R to the point H as shown.

The first and second input signals on lines 42 and 43 also connect through forward'diodes D and D to a junction point at which the wave form I will appear. B

voltage connects to the junction point I through the resistance R Inversion of the wave form J of FIGURE 4 is accom-.

circuit so that the output form will essentially constitute a sine wave of frequency corresponding to f voltage through resistance plished by'a simple inverting transistor Q together with resistances R and R and line 4-2 to provide the Wave form K at the junction point indicated by the letter K in FIGURE 5; Junction The junction pointsH and K in forward diodes D and D to a center line L at which the time modulated wave form L ofFIGURE 4 appears. This time modulated signal is then passed to the integrating circuit including the integrating transistor Q and storage condenser 41, the-operation and various elements making up the integrating circuit shown in FIGURE 5 being identical and designated by the same numerals and letters as the integrating circuitof FIGURE 3.

The operation of the circuit of FIGURE 5 to i s-at FI- "the foregoing description. A-and C are up, no conduc through resistance, R and through the reverse diodes D or D2. On the other hand, if either the input signal A or the input signal C is down, one or the other of the diodes D thereby causing a voltage drop across the resistance Rm to cause the signal at H to be down. Therefore, when both A and C are up, when either one or the other is down, or if both are down, the wave form at H will be down. These conditions are shown for the wave form H in FIGURE 4.

The same input signals A and C are also applied to the forward diodes D and D to provide the wave form J atthe junction point I. This wave form is down or at a low potential only when both waveforms A and C are down. Stated differently, if either or both wave form A or C is up, one or the other of the diodes D or D 'wi1l conduct across the resistance R to B1 therebycausing the wave form at the junction point I to be up. However, when both A and C are down, no conduction will take place across either diode D or B and therefore the wave form at the junction point I will be down or at B."

As mentioned above, the transistor Q; will simply invert the wave form appearingat I, conduction on the transistor Q occurring when I is down to cause junction point K to be up as the result of. voltage drop across resistance R Cutting off of the transistor when I isup results, in the the various waveforms described in connection with URE 4 will be evident from Thus, when both the signals tion can occur from B potentialat the junction point K being down as a con-.

1 one of the diodes D or D conducts since a voltage will 77 H and K, there is derived a time 'modulated signal L which is up when either H or K is diodes D 'and D on the V tions to the first and second switching transistors Q and .Q of FIGURE 3. Therefore, the diodes D D D and be developed across the resistance R On'the other hand, the wave form L will be down only when both diodes D and D are non-conducting, that is, when H and K are both down. It is evident, accordingly, that the wave form L can only be down when both H and K are down and at all other times will be up. a

Integration of the wave form L is exactly the same as integration of the wave form-E of FIGURE 2, but because of the polarity inversion of the wave form L as compared to the wave form E of FIGURE 2, the output integrated curve M will be 'of opposite polarity to the output integrated curve G; described in connection with FIGURE 2. However, the frequency of the output integrated wave form M will exactly correspond to the state determines conductions of diodes'D and D The other hand, serve similar func- D together with transistor Q may be identified as con point K is supplied with B+ turn connect through or D can conduct, f

the wave form H will be up, and

4 will be up when either diodes D and D andthe first and second control transistor Q and Q of FIGURE 3 insofar as their means having are open and 7 1 trol means and the diodes D as switching means.

, From the foregoing description, it will be evident that the present invention has provided extremely simple circuits for providing a difference frequency. Not only is the output signal limited to a single wave form having a difference frequency corresponding to the difference in the frequencies in first and second input signals, butin addition, there is no restriction on the actual difference frequency itself. In other words, by use of the integrating circuit, a D.C. output wave form could be provided if the difference frequency between the input wave forms corresponds to zero; that is, if the input wave forms had identically the same frequency.

While the various switching and control means have been effected through the use of transistors or diodes, it should be understood thatany equivalent switching means including even mechanical, relays 'could be employed although frequency limitations would be encountered with the use of mechanical relays in viewof their relativelyslow response time. 7 3

The present invention istherefore not to be thought of as limited to the specific embodiments set. forth merely for illustrative purposes. a

What is'claimed is: 7 V

1. A circuit for prov'ding an output wave form having a frequency equal to the difference in frequency between first and second input wave forms, including, in combination: square wave generating means connected to receive and convert said first and second input wave forms to first and second square wave forms; converting means connected to said square wave generating means to receive both said first and. second square wave forms and re- 7 square wave forms when of like polarity sponsive to said first given voltage and whenof-unlike for providing a polarity for providing a second given voltage; and intergrating means connected tosaid converting means to receive and integrate said first and second voltages to provide said output wave form, said converting means including a voltage source; first and second switching their inputs connected to said source and their outputs connected to said integrating means; and first and second control means connected to operate said first and second switching means, said first and'second control means being respectively connectedto receive said first and second square wave forms, one of said first and second given voltages being derived from said source at said integrating means when both of said switching means the other of said first and second given voltages being means when either one of said switching means is closed, said first and second control means opening and closing and D may be identified derived from said source at said integrating said switching means in accordance with the relative polarities of said first and second wave forms, said first and second switching means comprising front-to-front diodes respectively. with their common junction constituting said outputs connected to saidintegrating means and their backs constitutingsaid inputs connected to said voltage source, said firstand second control means comprising repectively; a first pair of reverse diodes having their fronts respectively connected to receive said first and second square wave forms and their backs connected to the input of said first switching means, and a second pair of forward diodes having their-backs respectively connected to receive said first and second square wave forms; an inverting transistor having its input connected to the fronts of said forward diodes and its output connected to the output of said second switch means, said first given voltage being derived from said sourceat said integrating means when either one of said switching means is closed and said second givenvoltage being derived from said source at said integrating means when both of said switching means are open, said first and second control means closing one of said switching means when said first and second Wave forms are of like polarity and opening both of said switching means when said first and second wave forms are of unlike polarity.

2. A circuit according to claiml, in which said square wave generating means, comprise overdriven amplifiers means includes a storage condenser discharging means connected to said condenser for changing the voltage across said condenser in one direction in response to the presence of said first voltage and changing the voltage across said condenser in an opposite direction in response to the presence of said second voltage, the amplitude of said output wave form varying injtime in a manner corresponding to substantially the voltage variation in time across said condenser.

and said integrating and a charging and References Cited by the Examiner UNITED STATES PATENTS 12/40 Bingley 328-28 XR 11/50 Miller 329-106 XR 3/59 Grisdale 307-885 12/60 Baskin et al. 324-89 XR 6/61 Leavitt 324-89 XR 6/61 Hall 307-885 .2/ 62 Kalmus et al. 324-83 7 JOHN w. HUCKERT, PrimaryExaminer.

HERMAN KARL SAALBACH, ARTHUR GAUSS,

Examiners. 

1. A CIRCUIT FOR PROVIDING AN OUTPUT WAVE FORM HAVING A FREQUENCY EQUAL TO THE DIFFERENCE IN FREQUENCY BETWEEN FIRST AND SECOND INPUT WAVE FORMS, INCLUDING, IN COMBINATION; SQUARE WAVE GENERTING MEANS CONNECTING TO RECEIVE AND CONVERT SAID FIRST AND SECOND INPUT WAVE FORMS TO FIRST AND SECOND SQUARE WAVE FORMS; CONVERTING MEANS CONNECTED TO SAID SQUARE WAVE GENERATING MEANS TO RECEIVE BOTH SAID FIRST AND SECOND SQUARE WAVE FORMS AND RESPONSIVE TO SAID SQUARE WAVE FORMS WHEN OF LIKE POLARITY FOR PROVIDING A FIRST GIVEN VOLTAGE AND WHEN OF UNLIKE POLARITY FOR PROVIDING A SECOND GIVEN VOLTAGE; AND INTEGRATING MEANS CONNECTED TO SAID CONVERTING MEANS TO RECEIVE AND INTEGRATE SAID FIRST AND SECOND VOLTAGES TO PROVIDE SAID OUTPUT WAVE FORM, SAID CONVERTING MEANS INCLUDING A VOLTAGE SOURCE; FIRST AND SECOND SWITCHING MEANS HAVING THEIR INPUTS CONNECTED TO SAID SOURCE AND THEIR OUTPUTS CONNECTED TO SAID INTEGRATING MEANS; AND FIRST AND SECOND CONTROL MEANS CONNECTED TO OPERATE SAID FIRST AND SECOND SWITCHING MEANS, SAID FIRST AND SECOND CONTROL MEANS BEING RESPECTIVELY CONNECTED TO RECEIVE SAID FIRST AND SECOND SQUARE WAVE FORMS, ONE OF SAID FIRST AND SECOND GIVEN VOLTAGES BEING DERIVED FROM SAID SOURCE AT SAID INTEGRATING MEANS WHEN BOTH OF SAID SWITCHING MEANS ARE OPEN AND THE OTHER OF SAID FIRST AND SECOND GIVEN VOLTAGES BEING DERIVED FROM SAID SOURCE AT SAID INTEGRATING MEANS WHEN EITHER ONE OF SAID SWITCHNG MEANS IS CLOSED, SAID FIRST AND SECOND CONTROL MEANS OPENING AND CLOSING SAID SWITCHING MEANS IN ACCORDANCE WITH THE RELATIVE POLARITIES OF SAID FIRST AND SECOND WAVE FORMS, SAID FIRST AND SECOND SWITCHING MEANS COMPRISING FRONT-TO-FRONT DIODES RESPECTIVELY WITH THEIR COMMON JUNCTION CONSTITUTING SAID OUTPUTS CONNECTED TO SAID INTEGRATING MEANS AND THEIR BACKS CONSTITUTING SAID INPUTS CONNECTED TO SAID VOLTAGE SOURCE, SAID FIRST AND SECOND CONTROL MEANS COMPRISING RESPECTIVELY, A FIRST PAIR OF REVERSE DIODES HAVING THEIR FRONTS RESPECTIVELY CONNECTED TO RECEIVE SAID FIRST AND SECOND SQUARE WAVE FORMS AND THEIR BACKS CONNECTED TO THE INPUT OF SAID FIRST SWITCHING MEANS, AND A SECOND PAIR OF FOWARD DIODES HAVING THEIR BACKS RESPECTIVELY CONNECTED TO RECEIVE SAID FIRST AND SECOND SQUARE WAVE FORMS; AN INVERTING TRANSISTOR HAVING ITS INPUT CONNCTED TO THE FRONTS OF SAID FORWARD DIODES AND ITS OUPUT CONNECTED TO THE OUTPUTS OF SAID SECOND SWITCH MEANS, SAID FIRST GIVEN VOLTAGE BEING DERIVED FROM SAID SOURCE AT SAID INTEGRATING MEANS WHEN EITHER ONE OF SAID SWITCHING MEANS IN CLOSED AND SAID SECOND GIVEN VOLTAGE BEING DERIVED FROM SAID SOURCE AT SAID INTEGRATING MEANS WHEN BOTH OF SAID SWITCHING MEANS ARE OPEN, SAID FIRST AND SECOND CONTROL MEANS CLOSING ONE OF SAID SWITCHING MEANS WHEN SAID FIRST AND SECOND WAVE FORMS ARE OR LIKE POLARITY AND OPENING BOTH OF SAID SWITCHING MEANS WHEN SAID FIRST AND SECOND WAVE FORMS ARE OF UNLIKE POLARITY. 